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AMD 10h
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#	Item
31	mhz: Anatomy of a micro-benchmark Carl Staelin Hewlett-Packard Laboratories Larry McVoy BitMover, Inc. Add to Reading List Source URL: www.bitmover.com Language: English - Date: 2012-05-31 15:59:02 Compiler optimization Cycles per instruction DEC Alpha PA-8000 Clock signal SunOS AMD 10h Intel 80486 Computer architecture Computer hardware SPARCstation
32	Techniques for Mitigating Memory Latency Effects in the PA-8500 Processor David Johnson Systems Technology Division Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 22:48:32 Computer architecture Computing CPU cache Cache PA-8000 R8000 AMD 10h Computer hardware Central processing unit Computer memory
33	UltraSPARC III: A 600 MHz 64-bit Superscalar Processor for 1000-Way Scalable Systems Bill Lynch Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 22:48:30 Cache Computer memory UltraSPARC III UltraSPARC II R8000 AMD 10h Computer hardware Central processing unit CPU cache
34	Performance Methodologies for Opteron Servers Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-28 00:09:43 Computer engineering Computing AMD 10h Advanced Micro Devices X86 Computer hardware
35	HOT CHIPS 2012 AMD “TRINITY” APU Sebastien Nussbaum AMD Fellow Trinity SOC Architect Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-28 00:25:24 Video cards Bulldozer Unified Video Decoder CPU cache Radeon Bobcat AMD 10h Computer hardware ATI Technologies Advanced Micro Devices
36	ENERGY-EFFICIENT THREAD-LEVEL SPECULATION CHIP MULTIPROCESSORS WITH THREAD-LEVEL SPECULATION HAVE BECOME THE SUBJECT OF INTENSE RESEARCH. THIS WORK REFUTES THE CLAIM THAT SUCH A DESIGN IS NECESSARILY TOO ENERGY INEFFICIE Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2006-02-09 23:08:49 Computing CPU cache Cache Microarchitecture Parallel computing AMD 10h Compiler optimization Central processing unit Computer hardware Computer architecture
37	Brief Announcement: Few Buffers, Many Hot Spots, and No Tree Saturation (with High Probability) Bradley C. Kuszmaul William Kuszmaul Add to Reading List Source URL: supertech.csail.mit.edu Language: English - Date: 2015-02-18 01:45:03 Ethernet Network switch AMD 10h
38	Rebound: Scalable Checkpointing for Coherent Shared Memory Rishi Agarwal, Pranav Garg, and Josep Torrellas University of Illinois at Urbana-Champaign, USA {agarwa29,garg11,torrella}@illinois.edu Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2011-04-01 11:24:25 Central processing unit Microprocessors Application checkpointing Computer memory Parallel computing CPU cache Multi-core processor AMD 10h Microarchitecture Computer architecture Computer hardware Computing
39	The Design Complexity of Program Undo Support in a General-Purpose Processor Radu Teodorescu and Josep Torrellas Department of Computer Science University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2005-10-16 18:49:08 Central processing unit Cache CPU cache Computer memory Microarchitecture AMD 10h Parallel computing LEON Speculative execution Computer hardware Computer architecture Computer engineering
40	Characterizing the Impact of End-System Affinities On the End-to-End Performance of High-Speed Flows Nathan Hanford1 , Vishal Ahuja1 , Mehmet Balman2 , Matthew K. Farrens1 , Dipak Ghosal1 , Eric Pouyoul2 and Brian Tierne Add to Reading List Source URL: www.es.net Language: English - Date: 2014-12-11 12:32:11 Computer memory Scheduling algorithms Microprocessors Computer architecture Multi-core processor Parallel computing AMD 10h Jumbo frame CPU cache Computing Computer hardware Concurrent computing

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